1. Field of the Invention
The present invention relates to a data processing device, more particularly, to a data processing device using an instruction prefetch system.
The processing speed of a data processing device, e.g., a microprocessor unit, has become much higher due to the use of pipeline processing, etc. In the pipeline process, however, a plurality of processes are carried out in parallel, and therefore, the speed is too slow to enable the data processing device to successively fetch instructions one by one from a storage portion by one process.
To solve this problem, "an instruction prefetch" is carried out, to increase the processing speed and thus avoiding a bottleneck in the processing of instructions. In the instruction prefetch, a plurality of continuous instructions are read from an external memory and stored to an internal instruction buffer, and an instruction to be processed is fetched from the buffer when necessary.
Note, in the processing by the data processing device, usually the continuous instructions are successively carried out in accordance with the address numbers thereof, but in a different kind of processing, a conditional branch processing is carried out. Namely, in the conditional branch processing, a condition of a conditional jump instruction is discriminated, and another instruction at another address is carried out when the condition of the conditional jump instruction is fulfilled. In such a conditional branch processing, an instruction to be carried out can not be stored in the buffer by a discriminated result of the conditional jump instruction, and therefore, in this case, the instruction must be fetched again from the external memory, and thus a bottleneck in the instruction processing occurs during the time required for this fetch and the processing speed is lowered.
2. Description of the Related Art
The conventional methods of conditional branch processing are indicated, for example, as follows:
(I) When a condition of a conditional jump instruction is not fulfilled by a discriminated result of the condition thereof, a next instruction is carried out. When a condition of a conditional jump instruction is fulfilled by a discriminated result of the condition of the conditional jump instruction, a prefetch instruction buffer is cleared and a destination instruction (branch-target instruction) of the conditional jump instruction is read from a memory and prefetched into the instruction buffer.
(II) A first prefetch instruction buffer and a second prefetch instruction buffer having the same capacities are provided, and in a normal state, one of the instruction buffers (for example, the first buffer) is used. When a conditional jump instruction is detected, a destination instruction is read from a memory and is stored to the second prefetch instruction buffer, and when a discriminated result of the condition thereof indicates a branch condition, the second prefetch instruction buffer is selected and the first prefetch instruction buffer is cleared. Conversely, when a discriminated result of the condition of the conditional jump instruction does not indicate a branch condition, the first prefetch instruction buffer is selected and the second prefetch instruction buffer is cleared.
(III) Furthermore, in the above case (II), one of the buffers is used as an exclusive prefetch instruction buffer and the capacity thereof is kept to a minimum, so that a hardware scale thereof is kept small.
In the case of (I), when the discriminated result of the condition of the conditional jump instruction is a branch condition, in this method the buffer must be cleared and a destination instruction read, and thus it is difficult for this method to avoid a bottleneck in the instruction processing. Next, in the case of (II), a bottleneck in an instruction processing can be avoided, but another problem arises in that two buffers having the same capacities must be provided, and thus the hardware scale thereof becomes very large.
On the other hand, in the case of (III), a bottleneck in an instruction processing can be avoided, and a hardware scale thereof kept to a minimum, since the capacity of the exclusive prefetch instruction buffer is determined by a destination instruction. Nevertheless, in this case (III), when conditional jump instructions are continued, for example, a condition of a first conditional jump instruction is fulfilled and a second conditional jump instruction appears, and just after instructions of the second conditional jump instruction are stored in the exclusive prefetch instruction buffer, it is difficult for this method to flexibly carry out these instructions. For example, if a condition of the second conditional jump instruction is not fulfilled, the just after instructions of the second conditional jump instruction should not be cleared, whereby the exclusive prefetch instruction buffer is not cleared and a destination instruction of the second conditional jump instruction cannot be fetched into the exclusive prefetch instruction buffer. Therefore, in this method the instructions from the exclusive prefetch instruction buffer must be transferred to a normal buffer, and thus it is difficult in this method to avoid a bottleneck in an instruction processing.
Furthermore, a branch instruction control system is provided for reducing the quantity of hardware, to decrease the delay and to realize a high-speed machine cycle by carrying out the prefetch control for a destination instruction while a branch instruction is being processed, as disclosed in Japanese Unexamined Pat. Publication No. 60-117336. But, in this Japanese Pat. Publication No. 60-117336, instructions read from an instruction memory means, e.g., a main memory or a instruction cache memory, are momentarily stored to a plurality of instruction word registers (IWR), the instruction word registers are connected directly to a multiplexer (MPX) and to the input of a plurality of instruction buffer registers (IBR), and the instructions stored in the IWR and IBR are selected by the MPX and applied to a pipeline system. In this branch instruction control system, however, the instructions are not written and read by using a write pointer and a read pointer as a register file configuration, but are written or read by using a shift register configuration. Therefore, the quantity of hardware in this branch instruction control system cannot be less than that needed when using a register file configuration.